Design of Low Power VLSI Circuits using Energy Efficient Adiabatic Logic
نویسندگان
چکیده
Abstract—In this paper, a new design of adiabatic circuit, called energy efficient adiabatic logic (EEAL) is proposed. Earlier various diode based adiabatic logic families have been proposed. To achieve minimum energy consumption, this paper proposes a technique in which diode is replaced by MOS transistor at charging and discharging path whose gate is controlled by the power clocks. By using this technique non adiabatic loss and power consumption of the diode is eliminated. In the proposed circuit, the input and output logic levels are nearly the same and can be used for building cascaded logic circuits. The split level sinusoidal power supply is used to achieve low power high speed adiabatic circuits. In this paper we have designed and simulated NOT, NAND, NOR gates, Half Adder and Full adder circuit. All simulations in this paper have been implemented by VIRTUOSO SPECTRE simulator of cadence with the 0.18 μm UMC technology MOS transistor model under 1.8-volt peak to peak split level sinusoidal power clock supply. From the simulation result, we find that proposed logic circuits can save significant amount of energy compared to CMOS circuits and GFCAL circuits with similar parameters up to 500MHz.
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